1. Field of the Invention
This invention relates to an MOS read-only memory device (hereinafter referred to as a ROM device) comprising MOS transistors.
2. Description of the Prior Art
Prior are MOS ROM devices are disclosed, for example, in Japanese Patent Publication Nos. 50-7896 and 57-13079, and Japanese Laid-open Patent Publication No. 56-165983. Such a MOS ROM device is illustrated in FIG. 1 and its arrangement will be explained in detail with reference to the accompanying drawing.
In FIG. 1, a prior art MOS ROM device having 8 words.times.(m+1) bits structure is shown which consists of a 3-input/8-output address decoder 1 and a NOR type memory cell matrix 2 having a 8 words.times.(m+1) bits structure.
The address decoder 1 has its inputs connected to address input terminals 3-1 to 3-2 and its output connected to word lines 4-0 to 4-6 and decodes the coded address signals A0 to A2 to select one of the word lines 4-0 to 4-6.
The memory cell matrix 2 has the word lines 4-0 to 4-6, the bit lines 5-0 to 5-m and a plurality if N-channel MOS transistors 6-00 to 6-6m connected at cross points of the word and bit lines. Each of the NMOS transistors 6-00 to 6-6m has its drain electrode connected to the bit line, its gate electrode connected to the word line and its source electrode grounded to Vss (0 volts).
The respective bit lines 5-1 to 5-m are connected at one end to P-channel MOS transistors 7-0 to 7-m and connected at the other end to sense circuits 8-0 to 8-m each comprising an inverter. The PMOS transistors have their drain electrodes connected to a source voltage VDD, and their gate electrodes connected to the ground potential VSS.
The sense circuits 8-0 to 8-m respectively have inputs connected to the bit lines 5-0 to 5-m and have output terminals 9-0 to 9-m and read out the signals on the bit lines 5-0 to 5-m to deliver output signals O0 to Om to their output terminals 9-0 to 9-m .
The operation of the prior art MOS ROM device is described below.
First, it is assumed that all of the MOS transistors 6-00, 6-0(m-1), 6-11, 6-30, 6-3m and 6-61 are in a written state.
When the address decoder 1 receives address signals A0 to A2, it, for example, selects the word line 4-9, whereby the word line 4-0 becomes an "H" level while the other word lines become an "L" level. As a result, only the MOS transistors 6-00 to 6-0(m-1) connected to the word line 4-0 are switched to make the bit lines 5-0 to 5-0(m-1) an "L" level, while the other bit lines 5-1 to 5-m become an "H" level. The sense circuits 8-0 to 8-m read the signals on the bit lines 5-0 to 5-m to output the inverted signals as output signals O0 to Om. In this case, the output signals O0 and O(m-1) become an "H" level while the other output signals become an "L" level.
However, the prior art ROM device has a disadvantage in that since a source current through MOS transistors associated with a selected word line flows during a read operation, power consumption is increased. In particular, a large scale memory cell matrix including a great number of bits to be selected significantly increases its power consumption during a read operation.